
COMMERCIALTEMPERATURERANGE
18
IDTCV115-2
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
PD#DE-ASSERTION
The time from the de-assertion of PD# or until power supply ramps to get stable clocks will be less than 1.8ms. If the drive mode control bit for PD# tristate
is programmed to ‘1’ the stopped differential pair must first be driven high to a minimum of 200mV in less than 300s of PD# deassertion.
PWRDWN#
CPU 133MHz
CPU# 133MHz
SRC 100MHz
SRC# 100MHz
USB 48MHz
PCI 33MHz
REF 14.31818
tSTABLE <1.8mS
tDRIVE_PWRDWN#
<300
μS, <200mV